DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER
DOI:
https://doi.org/10.29284/ijasis.4.2.2018.8-15Keywords:
FFT, SDF, Kogge stone parallel prefix adder, booth multiplier, XilinxAbstract
An efficient Fast Fourier Transform (FFT) algorithm is used in the Orthogonal Frequency Division Multiplexing (OFDM) applications in order to compute the discrete Fourier transform. Also, a Single Path Delay Feedback (SDF) which is pipeline FFT architecture is used for faster performance to achieve high throughput. In conventional method, the FFT design has high delay and power due to time taken by the multiplication part. To decrease the delay, Kogge Stone Parallel Prefix Adder (KSPPA) is used with booth multiplier. As SDF is a simpler approach to realize FFT in different length, 64-point Radix-4 SDF-FFT algorithm using KSPPA in the booth multiplier is discussed in this study. The system is implemented in Xilinx 12.4 ISE and simulated using MODELSIM 6.3c. Results show that the system reduces the delay and power.
Downloads
References
M.P.R. Bhonde, R.D. Ghongade, and R.D. Sushir, “Design and Simulation of 32 and 64 Point FFT Using Multiple Radix Algorithms”. Conference on Advanced Computing & Communication Technologies, Vol. 168, 2012, pp. 171.
C.F. Hsiao, Y. Chen, and C.Y. Lee, “A generalized mixed-radix algorithm for memory-based FFT processors”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.57, No.1, 2010, pp.26-30.
K. Ravi, and J. Lingaiah, “Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems”, International Journal of Scientific Engineering and Technology Research, Vol.5, No.38, 2016, pp.7960-7965.
C. Ingemarsson, P. Källström, F. Qureshi, and O. Gustafsson, “Efficient FPGA mapping of pipeline SDF FFT cores”, IEEE Transactions on Very Large Scale Integration Systems, Vol.25,No.9, 2017, pp.2486-2497.
H.L. Groginsky, and G.A. Works, “A pipeline fast Fourier transform”, IEEE Transactions on Computers, Vol.100,No.11, 1970, pp.1015-1019.
N.D. Vasumathy, and T. Vigneswaran, “A 128-Point FFT/IFFT Processor for MIMO-OFDM Transceivers–a Broader Survey”, International Journal of Engineering and Technology, Vol. 8,No.5, pp.2154-2160.
J. Agarwal, V. Matta, and D. Arya, “Design and implementation of FFT processor using Vedic multiplier with high throughput”, International journal of emerging technology and advanced engineering, Vol.3, No.10, 2013, pp.207-211.
G. Manikandan, and M. Anand, “Mixed Radix 4 & 8 Based SDF-SDC FFT Using MBSLS for Efficient Area Reduction”, Indian Journal of Public Health Research & Development, Vol. 9,No.10, 2018,pp.1112-1116
A.K. Singh, and A. Nandi, “Design of Four point Radix-2 FFT structure on Xilinx”, International Conference on Intelligent Computing and Control, 2017, pp. 1-4.
S.M. Joshi, “FFT architectures: a review”, International Journal of Computer applications, Vol.116, No. 7, 2015, pp.0975-8887.
K. Thabitha, and D. JayaKumar, “VLSI based 64-point pipelined FFT using radix-4 combined SDF-MDC”, International Journal of Pure and Applied Mathematics, Vol. 118, No. (20), pp.3509-3516.
O.A. Mukhanov, and A.F. Kirichenko, “Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders”, IEEE Transactions on Applied Superconductivity, Vol. 5, No.2, 1995, pp.2461-2464.
A. Rajaram, S. Saravanan, and R. Vijaysai, “Novel Design and Implementation of Fast Fourier Transform (FFT) Using Fast Adders”,Vol.5,No.2,2013,pp.542-546
M.B. Fonseca, E.A.C. da Costa, and J.B. Martins, “Design of power efficient butterflies from Radix-2 DIT FFT using adder compressors with a new XOR gate topology”, Analog Integrated Circuits and Signal Processing, Vol. 73,No. 3, 2012,pp.945-954.
K.H. Rao, and C. Paul,” Efficient Implementation of Radix 4 single path delay feedback (SDF) FFT Processors”. Indian Journal of Sciences and Technology, Vol. 9, No.12, 2016, pp.1-13.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
