SERIAL ADDER BASED MULTIPLICATION AND ACCUMULATION UNIT (MAC)
DOI:
https://doi.org/10.29284/ijasis.3.1.2017.25-30Keywords:
Finite Impulse Response (FIR) Filter, Adder, Multiplier, Multiplication and Accumulation (MAC) Unit, Multiplexer, Digital Signal Processing (DSP)Abstract
For efficient digital FIR filter applications, the Multiplication and Accumulation (MAC) unit is implemented by using various methods. In a digital filter, the MAC unit is one of the main units for performing multiplications and additions. This paper presents an efficient filter design for digital signal processing (DSP) applications with the reduction of carry propagation. In general, the performance of transpose filter mainly depends on the design of MAC unit. The design of a traditional filter consists of a large number of logical elements and has a high computational delay due to the conventional MAC unit. To design an efficient MAC unit, a serial adder is employed by using 2:1 multiplexer and a shifter block. The proposed work is implemented by using Xilinx ISE synthesis tool.
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H.K. Kwan, A multi-output first-order digital filter structure for VLSI implementation, IEEE Transactions on Circuits and Systems, Vol. 32 ,No. 9, 1985, pp. 973-974.
A. Huber, E. de Man, E. Schiller, and W. Ulbrich, FIR Lowpass filter for signal decimation with 15 MHz clock frequency, IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 11, 1986, pp. 1533-1536.
A.G. Dempster, and M.D. Macleod, Use of minimum-adder multiplier blocks in FIR digital filters IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 42, No. 9, 1995, pp. 569-577.
M.A. Soderstrand, L.G. Johnson, H. Arichathiran, M.D. Hoque, and R. Elangovan, Reducing hardware requirement in FIR filter design IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 6, 2000, pp. 3275-3278.
K. Nakamura, R. Yamanaka, T. Matsuda, and T. Harada, T, Recent developments in asymmetric reduction of ketones with biocatalysts, Tetrahedron: Asymmetry, Vol. 14, No. 18, pp. 2659-2681.
C. Cheng, and K.K. Parhi, Further complexity reduction of parallel FIR filters IEEE International Symposium on Circuits and Systems, 2005, pp. 1835-1838.
R. Conway, Reducing complexity of fixed-coefficient FIR filters Electronics Letters, Vol. 42 , No. 20, 2006, pp. 1185-1186.
C.H. Chang, J. Chen, and A.P. Vinod, Information theoretic approach to complexity reduction of FIR filter design IEEE Transactions on Circuits and Systems I, Vol. 55, No. 8, 2008, pp. 2310-2321.
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