A Deterministic Multiclass Odor Classification Architecture Using Weighted Hamming For Fpga Based Electronic Nose Systems
DOI:
https://doi.org/10.29284/9mfm8p20Keywords:
Electronic nose, Weighted Hamming similarity, Multiclass dense classification, FPGA implementation, Parallel reduction architecture.Abstract
Classification architectures that strike a balance between discriminative capability, stringent hardware efficiency, and deterministic execution are necessary for real-time odor recognition in embedded electronic nose systems. A dense multiclass classification framework based on weighted Hamming distance and designed for direct digital hardware realization is presented in this work. In order to compute similarity using bitwise logical operations, odor responses are encoded as fixed-length 72-bit binary feature vectors. To improve class separability while maintaining multiplier-free implementation, a feature-weighted extension of the classical Hamming metric is developed. In order to ensure latency limited by the combinational depth of XOR mismatch detection, integer accumulation, and comparator selection, the suggested architecture evaluates all stored class templates in parallel. The framework reduces logic depth and resource usage by doing away with floating-point operations and DSP-dependent multipliers, in contrast to arithmetic-intensive machine learning models. To confirm functional correctness and deterministic decision behavior, the design is validated using ModelSim simulation after being modeled at the register-transfer level in Verilog HDL. According to complexity analysis, hardware resources scale linearly with feature dimension and class count, while classification latency is constrained by combinational logic depth under fully parallel deployment. Instead of using post-synthesis FPGA measurements, the performance evaluation is based on analytical timing estimation and functional RTL simulation. For FPGA-oriented electronic nose classification systems that need consistent timing and computational efficiency, the resulting architecture offers a scalable and hardware-transparent substitute.
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This work is licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
