Edge-Optimized Neuromorphic VLSI Accelerator Based On Hybrid Spiking Neural Models

Authors

  • Ravi Shankar P Assistant Professor, Department of Mechatronics Engineering, Nehru Institute of Engineering and Technology, Coimbatore -641105
  • S. Balaji Assistant Professor, Department of Aeronautical Engineering, Nehru Institute of Engineering and Technology, Coimbatore-641105
  • Gokul C Professor, Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore-641021
  • K. Nagarajan Associate Professor, Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, Coimbatore-641105
  • A. Arulkumar Assistant Professor, Department of Electrical and Electronics Engineering, Nehru Institute of Engineering and Technology, Coimbatore-641105
  • S. Venkatesh Assistant Professor, Department of Computer Science Engineering, Nehru Institute of Engineering and Technology, Coimbatore- 641105

DOI:

https://doi.org/10.29284/ijasis.12.1.2026.199-210

Keywords:

Neuromorphic VLSI, Hybrid Spiking Neural Networks, Edge AI Accelerator, Low-Power Computing, Event-Driven Processing.

Abstract

The rapid proliferation of edge intelligence has created an urgent demand for ultra-low-power, high-performance hardware accelerators capable of executing complex AI workloads under stringent energy and latency constraints. This paper presents an edge-optimized neuromorphic VLSI accelerator based on hybrid spiking neural models, specifically designed to support real-time inference in resource-constrained edge environments. The proposed architecture integrates biologically inspired spiking neurons with conventional artificial neural processing units, enabling efficient event-driven computation and adaptive learning capabilities. A hybrid processing framework is introduced, combining rate-coded and temporal spiking mechanisms to enhance representational efficiency and inference accuracy while minimizing memory access overhead. The accelerator employs parallel spike routing, on-chip synaptic weight storage, and dynamic voltage-frequency scaling to achieve optimal energy efficiency. Hardware-aware optimizations, including sparsity exploitation and spike-driven computation scheduling, significantly reduce switching activity and power consumption. Post-layout simulations using a 45-nm CMOS technology demonstrate up to 62% reduction in power consumption and 1.8× improvement in throughput compared to conventional digital CNN accelerators. Experimental evaluation on benchmark datasets confirms competitive accuracy while achieving sub-millijoule energy per inference. The proposed design establishes a scalable and energy-efficient neuromorphic VLSI framework, making it highly suitable for next-generation edge AI applications such as IoT sensing, wearable devices, and autonomous systems.

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Published

2026-01-15

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Articles

How to Cite

[1]
R. Shankar P, S. Balaji, G. C, K. Nagarajan, A. Arulkumar, and S. Venkatesh, “Edge-Optimized Neuromorphic VLSI Accelerator Based On Hybrid Spiking Neural Models”, IJASIS, pp. 199–210, Jan. 2026, doi: 10.29284/ijasis.12.1.2026.199-210.

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