Blockchain-Enabled Secure VLSI Framework For Distributed Hardware Verification And IP Protection

Dr. V. T. Krishnaprasath; Dr. T. Surya; B. Suganthi; Mohammed Kasim M; Priya B; P. Priyadharsini

doi:10.29284/ijasis.12.1.2026.187-198

Authors

Dr. V. T. Krishnaprasath Associate Professor Department of Artificial Intelligence and Data Science Nehru Institute of Engineering and Technology Coimbatore, Tamil Nadu, India
Dr. T. Surya Assistant Professor Department of Electronics and Communication Engineering Akshaya College of Engineering and Technology Kinathukadavu, Coimbatore – 642109, Tamil Nadu, India
B. Suganthi Associate Professor – ECE RVS College of Engineering and Technology Coimbatore – 641402, Tamil Nadu, India
Mohammed Kasim M Assistant Professor (SG) Department of Electronics and Communication Engineering Nehru Institute of Engineering and Technology Coimbatore – 641105, Tamil Nadu, India
Priya B Assistant Professor Department of Computer Science and Business Systems Nehru Institute of Engineering and Technology Coimbatore, Tamil Nadu, India
P. Priyadharsini Assistant Professor Department of Information Technology Nehru Institute of Engineering and Technology Coimbatore, Tamil Nadu, India

DOI:

https://doi.org/10.29284/ijasis.12.1.2026.187-198

Keywords:

Blockchain, Secure VLSI, Hardware Verification, IP Protection, Hardware Provenance, Smart Contracts, Permissioned Ledger, Distributed Design Flow, Tamper-Evident Audit, Anti-Counterfeiting, Trojan Resistance, Design Integrity, Secure EDA.

Abstract

The globalization of semiconductor supply chains and the rise of third-party IP reuse have intensified concerns around hardware Trojan insertion, counterfeit IP distribution, unauthorized overbuilding, and dispute-prone verification workflows in modern VLSI design. This paper proposes a Blockchain-Enabled Secure VLSI Framework that unifies distributed hardware verification, provenance tracking, and IP protection through tamper-evident ledger records and cryptographically verifiable design artifacts. The proposed framework registers RTL/netlist milestones, verification reports, test signatures, and PDK-dependent constraints as immutable transactions, enabling all stakeholders (IP vendors, integrators, foundries, and verification labs) to validate authenticity and integrity without exposing sensitive design content. To prevent IP leakage, the framework supports hash-anchored commitments, permissioned access control, and zero-knowledge–ready attestations for key verification claims (e.g., “coverage ≥ threshold” or “equivalence passed”) while keeping raw waveforms and proprietary constraints off-chain. A smart-contract policy engine enforces licensing (time-bound/feature-bound), audit logging, and revocation, while a lightweight on-chain/off-chain storage strategy ensures scalability. Analytical evaluation and prototype-level profiling indicate that the approach can provide end-to-end traceability with sub-second block confirmation in permissioned mode, ~25–45% reduction in dispute resolution time via automated audit trails, and ~15–30% lower manual compliance effort by standardizing verification evidence exchange. The framework is suitable for secure SoC integration, multi-vendor verification, and IP lifecycle governance in advanced VLSI flows.

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