Cross-Technology Evaluation of a Gate-Diffusion-Input Magnitude Comparator for Scalable CMOS Architectures
DOI:
https://doi.org/10.29284/ijasis.12.1.2026.104-123Keywords:
Gate Diffusion Input (GDI); magnitude comparator; CMOS scaling; low-power VLSI; nanometer technology; propagation delay; power-delay product (PDP); circuit optimization; energy-efficient digital design; Tanner EDA simulation.Abstract
As modern digital systems demand enhanced computational efficiency under stringent power and area constraints, comparator circuits play a critical role in arithmetic and decision-making units. This paper presents a comprehensive cross-technology analysis of a Gate Diffusion Input (GDI)-based magnitude comparator implemented across multiple nanometer CMOS process nodes (180 nm, 90 nm, 45 nm, and 22 nm). The proposed design leverages the GDI technique to minimize transistor count, reduce static power dissipation, and improve switching performance compared to conventional CMOS and pass transistor logic structures. The comparator’s structural optimization focuses on reducing logic redundancy while maintaining full-swing operation and high noise immunity. Simulation studies were conducted using Cadence Virtuoso and Tanner EDA tools, employing BSIM4 technology models for accurate device-level characterization. Key performance parameters—including propagation delay, power consumption, power-delay product (PDP), and area utilization—were evaluated and compared across technology nodes. Results indicate that the proposed GDI-based design achieves a 47.3% reduction in average power, 38.6% improvement in speed, and 52.1% lower PDP compared to traditional CMOS comparators in 22 nm technology. Moreover, the design demonstrates strong scalability and energy efficiency, making it suitable for integration into low-power VLSI systems, signal processing units, and embedded architectures. This cross-node analysis establishes GDI logic as a viable alternative for high-performance, power-efficient comparator design in emerging nanoscale technologies.
References
1. Joy, U.B., Chakraborty, A., Biswas, P., Das, A., Sen, S. and Tasnim, A., 2023, January. Two-Bit Magnitude Comparator Design Using Gate Diffusion Input Technique and Static CMOS Logic. In 2023 3rd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST) (pp. 17-21). IEEE.
2. Beaulieu, P.O., Nabki, F. and Boukadoum, M., 2022, October. 8-bit partial magnitude comparator for spike generation in the leaky integrate-and-fire neuron model using gate-diffusion-input logic gates. In 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (pp. 1-4). IEEE.
3. Sindhuja, R., John Alex, E. and Niranjan Reddy, K., 2024, June. Efficient Two-Bit Magnitude Comparator with Hybrid Logic Approach. In International Conference on Soft Computing and Signal Processing (pp. 629-644). Singapore: Springer Nature Singapore.
4. Morgenshtein, A., Shwartz, I. and Fish, A., 2010, November. Gate diffusion input (GDI) logic in standard CMOS nanoscale process. In 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel (pp. 000776-000780). IEEE.
5. Biswas, S., Mukherjee, D.N., Panda, S. and Maji, B., 2021. Power efficient magnitude comparator using adiabatic logic and gate diffusion technique. In Advances in Medical Physics and Healthcare Engineering: Proceedings of AMPHE 2020 (pp. 207-213). Singapore: Springer Singapore.
6. D. Paulraj, L. R, T. Jayasudha, M. Ishwarya Niranjana, T. Daniya and F. Daniel Shadrach, "Blockchain-based Wireless Sensor Network Security Through Authentication and Cluster Head Selection," 2023 IEEE International Conference on Integrated Circuits and Communication Systems (ICICACS), Raichur, India, 2023, pp. 1-5, doi: 10.1109/ICICACS57338.2023.10099593.
7. K. Karthikeyan, V. Parthipan, M. I. Niranjana, D. Prithvi, N. R. Franklin and N. Kaviarasu, "Enhancing Vehicular Communication Efficiency Through DSRC and LTE-V2x Integration," 2024 International Conference on Science Technology Engineering and Management (ICSTEM), Coimbatore, India, 2024, pp. 1-6, doi: 10.1109/ICSTEM61137.2024.10560623.
8. K.Kalpana., Dr.B.Paulchamy, et.al “ Design and performance Analysis of Low power High Speed Adder and Multiplier Using MTCMOS in 90nm,25nmand 18nm Regime” , Journal of Advances in Parallel Computing, Under the topic of Smart Intelligent Computing &Communication technology, IOS Press, Volume :38, October 2021.
9. Venishetty, S.R. and Chidra, A.K., 2021. Design of power efficient, high-speed 4-bit comparator in UMC 180 nm technology. Engineering and Applied Science Research, 48(1), pp.40-47.
10. Abiri, E. and Darabi, A., 2020. Reversible logic-based magnitude comparator (RMC) circuit using modified-GDI technique for motion detection applications in image processing. Microprocessors and Microsystems, 72, p.102928.
11. Jayasanthi, M., Harini, K.S. and Vallisa, R., 2025, August. Power-Efficient Multiplier: Leveraging Approximate Designs and Modified Gate Diffusion Technique. In 2025 International Conference on Next Generation Computing Systems (ICNGCS) (pp. 1-7). IEEE.
12. Rafiee, M., Shiri, N., Sadeghi, A., Darabi, A. and Abiri, E., 2022. Low-power and fast-swing-restoration GDI-based magnitude comparator for digital images processing. Circuits, Systems, and Signal Processing, 41(9), pp.4848-4885.
13. Chaddha, K.K. and Chandel, R., 2010. Design and analysis of a modified low power CMOS full adder using gate-diffusion input technique. Journal of low power electronics, 6(4), pp.482-490.
14. Kumar, N.V. and Lloyd, F.V., 2025, September. A Novel Approach to Low Power Multiplier and Comparator Design using GDI Logic. In 2025 4th International Conference on Innovative Mechanisms for Industry Applications (ICIMIA) (pp. 46-51). IEEE.
15. Garg, A. and Joshi, G., 2018. Gate diffusion input based 4‐bit Vedic multiplier design. IET Circuits, Devices & Systems, 12(6), pp.764-770.
16. Murugesan, K.S. and Prathika, M.E., 2025, August. Design and Implementation of Low Power Parallel Transposed FIR Filter Using Modified Gate Diffusion Input Technique. In 2025 9th International Conference on Inventive Systems and Control (ICISC) (pp. 1594-1599). IEEE.
17. Madhav, C.H. and Syed, S.U., 2014. Low Transistor Count Scalable Digital Comparator. International Journal of Engineering Development and Research, 2(4), pp.3713-3717.
18. Deymad, S.F., Shiri, N. and Pesaran, F., 2023. High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics. Microelectronics Journal, 142, p.105972.
19. Oommen, R., George, M.K. and Joseph, S., 2018, December. Study and analysis of various LFSR architectures. In 2018 International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET) (pp. 1-6). IEEE.
20. Kumar, P.S., Snehalatha, G., Moinuddin, M.K., Manishankar, G. and Reddy, S.S.H., 2025, August. Machine Learning Assisted Optimization of Hybrid Full Adder based 4-bit Digital Comparator. In 2025 3rd International Conference on Sustainable Computing and Data Communication Systems (ICSCDS) (pp. 1931-1936). IEEE.
21. Saji, J. and Kamal, S., 2017. GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology. Microprocessors and Microsystems, 49, pp.18-27.
22. Hussain, S.A., Bevara, V. and Sanki, P.K., 2022, December. A high-speed low-power CMOS-memristor based hybrid comparator using m_GDI technique for IoT applications. In 2022 IEEE International Symposium on Smart Electronic Systems (iSES) (pp. 631-634). IEEE.
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This work is licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
