Design Of Ultra-Low-Power VLSI Circuitry For Wearable Retinal Image Monitoring Systems

Dr. Navin M. George; Dr. Ravikanth Garladinne; Dr.R. Sundar; S. Suganya; T. Balamani; Sreejith A. R

doi:10.29284/ijasis.12.1.2026.63-82

Authors

Dr. Navin M. George Associate Professor, Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India.
Dr. Ravikanth Garladinne Professor, Department of Computer Science and Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India.
Dr.R. Sundar Associate Professor, Department of Computer Science and Engineering, Vel Tech Rangarajan Dr.Sagunthala R&D Institute of Science and Technology ,Avadi, Chennai, Tamilnadu, India.
S. Suganya Assistant Professor, Department of Electronics and Communication Engineering, Hindusthan Institute of Technology, Coimbatore, Tamil Nadu, India.
T. Balamani Assistant Professor, Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore, Tamil Nadu, India.
Sreejith A. R Assistant Professor, Department of Electronics and Communication Engineering, V.S.B. College of Engineering Technical Campus, Coimbatore, Tamil Nadu, India

DOI:

https://doi.org/10.29284/ijasis.12.1.2026.63-82

Keywords:

VLSI design; wearable biomedical systems; retinal image monitoring; low-power circuits; sub-threshold CMOS; approximate computing; DWT compression; analog front-end; real-time imaging; tele-ophthalmology.

Abstract

Wearable biomedical devices have gained increasing prominence for continuous health monitoring and early disease diagnosis. Among these, retinal image monitoring systems play a crucial role in the detection of ophthalmic disorders such as diabetic retinopathy and glaucoma. However, the integration of advanced image sensors and processing units in wearable platforms is constrained by strict power, area, and performance requirements. This paper presents an ultra-low-power VLSI architecture specifically designed for wearable retinal image monitoring systems, achieving optimal trade-offs between energy efficiency, image quality, and real-time performance. The proposed design incorporates sub-threshold CMOS operation, adaptive clock gating, and approximate arithmetic units to minimize dynamic and leakage power consumption. A compressed sensing-based data acquisition module reduces redundant pixel sampling, while an on-chip image compression engine leverages Discrete Wavelet Transform (DWT) for efficient transmission with minimal loss of diagnostic information. The architecture also integrates a low-power analog front-end (AFE) for sensor readout and a digital co-processor for feature extraction, optimized through pipelined and parallelized datapaths. The system was synthesized using 45 nm CMOS technology in Cadence Virtuoso, achieving 42% lower power consumption, 25% area reduction, and a processing throughput of 80 frames per second compared to conventional designs. Experimental evaluations on retinal image datasets demonstrate preserved diagnostic fidelity with negligible degradation in signal-to-noise ratio (SNR). The proposed framework is ideal for next-generation portable ophthalmic screening and telemedicine applications, contributing to the development of energy-aware wearable biomedical vision systems.

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