VLSI Architecture for Energy-Efficient Convolutional Neural Networks in Embedded Image Recognition Systems

Authors

  • Dr. V. Jayaraj Professor and Head, Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India.
  • B. Tamil Selvi Assistant Professor, Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore, Tamil Nadu, India.
  • Dr. A. Udhayakumar Associate Professor, Department of Electronics and Communication Engineering, V.S.B. College of Engineering Technical Campus, Coimbatore, Tamil Nadu, India.
  • Dr. J. Dhanasekar Assistant Professor, Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, Tamil Nadu, India.
  • Dr. P. Jayashree Associate Professor, Department of Electronics and Communication Engineering, Nandha Engineering College, Perundurai, Erode, Tamil Nadu, India.
  • Dr. A. Kishore Kumar Associate Professor, Department of Robotics and Automation, Sri Ramakrishna Engineering College, Coimbatore, Tamil Nadu, India.

DOI:

https://doi.org/10.29284/ijasis.12.1.2026.46-62

Keywords:

VLSI architecture; convolutional neural network (CNN); energy efficiency; approximate computing; embedded vision; reconfigurable processing elements; MAC optimization; quantization; low-power design; edge intelligence.

Abstract

The integration of Convolutional Neural Networks (CNNs) in embedded vision systems demands a careful balance between computational efficiency, power consumption, and on-chip memory utilization. This paper presents a novel energy-efficient VLSI architecture optimized for CNN-based image recognition in resource-constrained embedded platforms. The proposed design employs approximate arithmetic computing, clock gating, and data reuse optimization to achieve significant energy savings without compromising recognition accuracy. The architecture introduces a reconfigurable processing element (RPE) array with shared weight buffers and hierarchical memory control to minimize data movement between layers. A pipelined convolutional engine combined with quantized 8-bit fixed-point operations reduces both dynamic power and hardware complexity. Additionally, a parallel multiplier–accumulator (MAC) optimization is incorporated using a modified Booth algorithm for faster convolution and reduced latency. Implemented in 45 nm CMOS technology using Cadence and Synopsys Design Compiler, the proposed architecture achieves a 35% reduction in power, 28% lower area utilization, and 40% improvement in throughput compared to conventional CNN accelerators. When deployed on embedded benchmarks such as CIFAR-10 and MNIST, the system attains a classification accuracy of 98.3% with a peak energy efficiency of 1.26 TOPS/W. The design demonstrates excellent scalability and suitability for edge-based visual intelligence applications such as drones, surveillance, and IoT-enabled smart devices.

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Published

2026-01-15

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Section

Articles

How to Cite

[1]
D. V. Jayaraj, B. T. Selvi, D. A. Udhayakumar, D. J. Dhanasekar, D. P. Jayashree, and D. A. K. Kumar, “VLSI Architecture for Energy-Efficient Convolutional Neural Networks in Embedded Image Recognition Systems”, IJASIS, pp. 46–62, Jan. 2026, doi: 10.29284/ijasis.12.1.2026.46-62.

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