LOW POWER CIRCUIT FOR BRENT-KUNG ADDER BASED ON ADIABATIC LOGIC
DOI:
https://doi.org/10.29284/ijasis.4.1.2018.8-15Keywords:
CMOS, Brent-kung adder, adiabatic logic, Tanner EDAAbstract
Adiabatic logic circuit designs are used to reduce power dissipation in any circuits. For low power and low noise emission applications, adder plays a vital role. The Complementary Metal Oxide Semiconductor (CMOS) design of 16-bit Brent-kung adder provides less number of gates but it generates high power due to switching activities of the design. To overcome this problem, 16-bit Brent-kung adder is designed using complementary Pass Transistor Energy Recovery adiabatic Logic (CPERL) with less number of gates. Also, low power dissipation is achieved which can be used for long life battery operations. The CPERL based system offers 59.97% reduction in power when compared to the conventional design. Experimental results are obtained using TANNER EDA tool 13.1.
References
A. Dave, “A novel Adiabatic SRAM design using Two Level Adiabatic Logic”. Biennial Baltic Electronics Conference, 2016, pp. 51-54.
V. Bindal, ”Adiabatic Logic Circuit Design”, International Journal of Innovative Science, Engineering & Technology, Vol. 3, No. 3, 2016, pp.688-694.
G.P.S. Prashanti, N.N. Sirisha, and N.A. Reddy, “Low Power Adiabatic Logic Design”, IOSR Journal of Electronics and Communication Engineering, Vol. 12, No. 1, 2017, pp.28-34.
V. Anantharam, M. He, K. Natarajan, H. Xie, and M.P. Frank, “Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators”, ESA/VLSI, 2004 , pp.5-11.
R.C. Chang, P.C. Hung, and I.H. Wang, “Complementary pass-transistor energy recovery logic for low-power applications”, IEE Proceedings-Computers and Digital Techniques, Vol. 149, No.4, 2002, pp.146-151.
G.R. Tulasi, K. Venugopal, B. Vijayabaskar, and R. SuryaPrakash, “Design & Analysis of full adders using adiabatic logic”, International Journal of Engineering Research & Technology, Vol. 1,No. 5, 2012, pp.1-5.
A. Vetuli, S. Pascoli, and L.M. Reyneri, “Positive feedback in adiabatic logic”, IEEE Electronics Letters, Vol. 32, No.20, 1996, pp.1867-1869.
D. Maksimovic, V.G. Oklobdzija, B. Nikolic, and K.W. Current, “Clocked CMOS adiabatic logic with integrated single-phase power-clock supply”, IEEE Transactions on Very Large Scale Integration Systems, Vol. 8,No. 4, 2000, pp.460-463.
Y. Takahashi, Y. Fukuta, T. Sekine, and M. Yokoyama, “2PADCL: Two phase drive adiabatic dynamic CMOS logic”, IEEE Asia Pacific Conference on Circuits and Systems, 2006, pp. 1484-1487.
E. Amirante, A. Bargagli-Stoffi, J. Fischer, G. Iannaccone, and D. Schmitt-Landsiedel, “Variations of the power dissipation in adiabatic logic gates”, International Workshop on Power And Timing Modeling, Optimization and Simulation, Vol. 1, 2001, pp. 9-1.
N.S.S. Reddy, M. Satyam, and K.L. Kishore, “Cascadable adiabatic logic circuits for low-power applications”, IET circuits, devices & systems, Vol. 2,No. 6, 2008, pp.518-526.
H. Shekhar, “Design Of Low Power Novel Gate”, International journal of advances in signal and image sciences”, Vol. 2,No.1, 2016,pp.19-23.
J. Lim, K. Kwon, and S.I. Chae, “Reversible energy recovery logic circuit without non-adiabatic energy loss”, Electronics Letters, Vol. 34,No. 4, 1998, pp.344-345.
N. Liao, X. Cui, K. Liao, K. Ma, D. Wu, W. Wei, R. Li, and D. Yu, “Low power adiabatic logic based on FinFETs”, Science China information sciences, Vol. 57,No. 2, 2014,pp.1-13.
N. Desai, “Design Of High Performance 16-Bit Brent Kung Adder Using Static CMOS Logic Style In 45nm CMOS NCSU Free Pdk”, IRAJ International Conference, 2013, pp.31-33.
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