Energy-Efficient Reconfigurable Vlsi Accelerator For On-Device Ai In Massive Mimo Communication

Jyoti Kumari; Swati Kumari; Dipshikha Narayan; Shashi Kumar; Lucky Kumar

doi:10.29284/t063kv30

Authors

Jyoti Kumari Assistant Professor, Department of Electronics and Communication Engineering Government Engineering College Nawada
Swati Kumari Assistant Professor, Department of Electronics and Communication Engineering Gaya College of Engineering Gayaji
Dipshikha Narayan Assistant Professor, Department of Electronics and Communication Engineering Government Engineering College West Champaran
Shashi Kumar Assistant Professor, Department of Electronics and Communication Engineering Government Engineering College Nawada
Lucky Kumar Assistant Professor, Department of Electronics and Communication Engineering Government Engineering College Nawada

DOI:

https://doi.org/10.29284/t063kv30

Keywords:

VLSI accelerator, massive MIMO, on-device AI, reconfigurable computing, energy efficiency, beamforming, DVFS, systolic array, 5G/6G.

Abstract

The exponential growth of antenna arrays in fifth-generation (5G) and emerging sixth-generation (6G) networks introduces severe computational demands for real-time signal processing, particularly in massive multiple-input multiple-output (MIMO) systems. Conventional general-purpose processors and field-programmable gate arrays fail to simultaneously satisfy the latency, throughput, and energy constraints demanded by on-device AI-assisted beamforming and channel estimation tasks. This paper presents a novel reconfigurable VLSI accelerator implemented in 28 nm CMOS technology that integrates a 256×256 systolic processing array, a dynamically voltage-frequency-scaled (DVFS) power management unit, and a sparse neural network inference engine optimized for massive MIMO workloads. The proposed architecture achieves a peak throughput of 41.6 tera-operations per second (TOPS) with an energy efficiency of 28.7 TOPS/W, representing a 2.9× improvement over the best-reported prior ASIC designs. Simulation results over 256-antenna, 64-user configurations confirm that the embedded AI detector yields bit-error-rate (BER) performance within 0.7 dB of the maximum-likelihood bound, while sustaining a total chip power of 4.7 W. The design is validated through post-layout simulation and gate-level verification, confirming its suitability for next-generation base-station and edge-AI deployments.

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