Unified Optimization Strategies for CNN and SVM Hardware Accelerators on Reconfigurable FPGA Architectures
DOI:
https://doi.org/10.29284/1d067457Keywords:
CNN; FPGAs; GPUs; ML Workloads; RBF; SVMAbstract
The rapid growth of machine learning applications and the increasing complexity of neural network architectures have created a pressing need for specialized hardware solutions that can deliver efficient execution of computationally intensive ML workloads. Traditional general-purpose processors will always have a general-use perspective, based on the sequential processing model of the von Neumann architecture, when handling the large number of parallel computations associated with modern machine learning algorithms. This paper provides a thorough examination of hardware acceleration strategies for improving machine learning performance, tracing the evolution from traditional CPUs to dedicated hardware accelerators. It examines various hardware acceleration approaches, starting with Graphics Processing Units (GPUs), which leverage their massively parallel architecture to accelerate the matrix operations and Field-Programmable Gate Arrays (FPGAs), which provide a flexible middle ground that can be configured into custom hardware optimized for the architecture of a specific neural network while remaining adaptable to any future hardware updates in the underlying machine learning framework algorithms. The analysis identified that the best hardware acceleration implementations rely heavily on the specific use case, with training workloads requiring different optimizations than inference workloads. In conclusion, this comprehensive investigation provides an important resource for researchers, engineering professionals, and decision makers navigating the rapidly evolving market of machine learning and hardware acceleration. It offers practical guidance and support for choosing and deploying acceleration solutions that balance performance, energy efficiency, cost, and programmability.
References
[1] K. Irick, M. DeBole, V. Narayanan and A. Gayasen, “A hardware efficient support vector machine
architecture for FPGA,” Proceedings of the 16th International Symposium on Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2008, pp. 304–305, Published by IEEE, DOI:
10.1109/FCCM.2008.26, Available: https://ieeexplore.ieee.org/document/4724927.
[2] C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao and J. Cong, “Optimizing FPGA-based accelerator design
for deep convolutional neural networks,” Proceedings of the ACM/SIGDA International Symposium
on Field-Programmable Gate Arrays, ACM, February 2015, Vol. 2015, pp. 161–170, Published by
ACM, DOI: 10.1145/2684746.2689060.
[3] K. Simonyan and A. Zisserman, “Very deep convolutional networks for large-scale image
recognition,” arXiv preprint, 10 April 2015, arXiv:1409.1556, DOI: 10.48550/arXiv.1409.1556,
Available: https://arxiv.org/abs/1409.1556.
[4] A. Krizhevsky, I. Sutskever and G. E. Hinton, “ImageNet classification with deep convolutional
neural networks,” Communications of the ACM, Print ISSN: 0001-0782, Online ISSN: 1557-7317,
May 2017, Vol. 60, No. 6, pp. 84–90, Published by ACM, DOI: .
[5] C. Szegedy, W. Liu, Y. Jia, P. Sermanet, S. Reed, et al., “Going deeper with convolutions,” Proceedings
of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), IEEE, June
2015, pp. 1–9, Published by IEEE, DOI: 10.1109/CVPR.2015.7298594.
[6] K. He, X. Zhang, S. Ren and J. Sun, “Deep residual learning for image recognition,” Proceedings
of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), IEEE, June 2016, pp.
770–778, Published by IEEE, DOI: 10.1109/CVPR.2016.90.
[7] S. Han, X. Liu, H. Mao, J. Pu, A. Pedram, et al., “EIE: Efficient inference engine on compressed
deep neural networks,” ACM SIGARCH Computer Architecture News, Print ISSN: 0163-5964, October
2016, Vol. 44, No. 3, pp. 243–254, Published by ACM, DOI: 10.1145/3007787.3001163.
[8] M. Papadonikolakis and C.-S. Bouganis, “Novel cascade FPGA accelerator for support vector
machines classification,” IEEE Transactions on Neural Networks and Learning Systems, Print ISSN:
2162-237X, July 2012, Vol. 23, No. 7, pp. 1040–1052, Published by IEEE, DOI:
10.1109/TNNLS.2012.2196446.
[9] C. Kyrkou, T. Theocharides and C.-S. Bouganis, “An embedded hardware-efficient architecture
for real-time cascade support vector machine classification,” Proceedings of the International Conference
on Embedded Computer Systems (SAMOS), IEEE, July 2013, pp. 129–136, Published by
IEEE, DOI: 10.1109/SAMOS.2013.6621115.
[10] S. Shao, O. Mencer and W. Luk, “Dataflow design for optimal incremental SVM training,” Proceedings
of the International Conference on Field-Programmable Technology (FPT), IEEE, December
2016, pp. 197–200, Published by IEEE, DOI: 10.1109/FPT.2016.7929532.
[11] S. Ren, K. He, R. Girshick and J. Sun, “Faster R-CNN: Towards real-time object detection with
region proposal networks,” Advances in Neural Information Processing Systems, December 2015,
Vol. 28, pp. 91–99, Published by NeurIPS Foundation, Available: https://proceedings.neurips.
cc/paper/2015.
[12] R. Zhao, X. Niu, Y. Wu, W. Luk and Q. Liu, “Optimizing CNN-based object detection algorithms
on embedded FPGA platforms,” Lecture Notes in Computer Science, Springer, 2017, Vol. 10216, pp.
255–267, Published by Springer, DOI: 10.1007/978-3-319-56258-2_22.
[13] J. Redmon, S. Divvala, R. Girshick and A. Farhadi, “You only look once: Unified, real-time object
detection,” Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition
(CVPR), IEEE, June 2016, pp. 779–788, Published by IEEE, DOI:
https://doi.org/10.1109/CVPR.2016.91
[14] S. Wang, X. Niu, N. Ma, W. Luk, P. Leong, et al., “A scalable dataflow accelerator for real-time
onboard hyperspectral image classification,” Lecture Notes in Computer Science, Springer, 2016,
Vol. 9625, pp. 105–116, Published by Springer, DOI: 10.1007/978-3-319-30481-6_9.
[15] M. Kurek, M. P. Deisenroth, W. Luk and T. Todman, “Knowledge transfer in automatic optimisation
of reconfigurable designs,” Proceedings of the IEEE Symposium on Field-Programmable
Custom Computing Machines, IEEE, 2016, pp. 84–87, Published by IEEE, DOI:
https://doi.org/10.1109/FCCM.2016.29
[16] F. Melgani and L. Bruzzone, “Classification of hyperspectral remote sensing images with support
vector machines,” IEEE Transactions on Geoscience and Remote Sensing, Print ISSN: 0196-
2892, August 2004, Vol. 42, No. 8, pp. 1778–1790, Published by IEEE, DOI:
https://doi.org/10.1109/TGRS.2004.831865
[17] S. Williams, A. Waterman and D. Patterson, “Roofline: An insightful visual performance model
for multicore architectures,” Communications of the ACM, Print ISSN: 0001-0782, April 2009, Vol.
52, No. 4, pp. 65–76, Published by ACM, DOI: 10.1145/1498765.1498785.
[18] J. Qiu, J. Wang, S. Yao, K. Li, B. Yu, T. Tang, N. Xu, S. Song, Y. Wang and H. Yang, “Going deeper
with embedded FPGA platform for convolutional neural network,” Proceedings of the ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays, ACM, February 2016, pp. 26–35,
Published by ACM, DOI: 10.1145/2847263.2847265.
[19] C. Guo, H. Fu and W. Luk, “A fully-pipelined expectation-maximization engine for Gaussian
mixture models,” Proceedings of the International Conference on Field-Programmable Technology,
IEEE, 2012, pp. 182–189, Published by IEEE, DOI: https://doi.org/10.1109/FPT.2012.6412132
[20] Y. Umuroglu, N. J. Fraser, G. Gambardella, M. Blott, P. Leong, et al., “FINN: A framework for
fast, scalable binarized neural network inference,” Proceedings of the ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays, ACM, February 2017, pp. 65–74, Published by
ACM, DOI: 10.1145/3020078.3021744.
[21] R. Zhao, T. Todman, W. Luk and X. Niu, “DeepPump: Multi-pumping deep neural networks,”
Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures
and Processors, IEEE, 2017, p. 206, Published by IEEE. DOI:
https://doi.org/10.1109/ASAP.2017.7995281
[22] M. Pandey, J. S. Ubhi and K. S. Raju, “Computational acceleration of real-time kernel-based
tracking system,” Journal of Circuits, Systems and Computers, Print ISSN: 0218-1266, April 2016,
Vol. 25, No. 04, p. 1650030, Published by World Scientific, DOI: 10.1142/S0218126616500304.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
This work is licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
