QCA DESIGN FOR 4-BIT ASYNCHRONOUS DOWN COUNTER

: Quantum Cellular Automata (QCA) is a transistor-less computation model that addresses the problem of device interconnection and density which holds the promise of high speed and fewer sizes compare to the Complementary Metal Oxide Semiconductor (CMOS) design. In this study, the design of 4-bit down asynchronous counter which is the fundamental block of the digital technology using new D-Flip Flops (D-FF) layouts is discussed. This D-FF is designed using majority gates. The FF clock inputs are not driven by the same clock and each FF output depends on the previous output. This design finds its application in nanotechnology fields including medical field to monitor the patient‟s activity by utilizing timer based tools. The design of 4-bit down asynchronous counter is simulated in the QCA design tool.


I. INTRODUCTION
QCA systems consist of arrays of interacting cells.Each cell affects its neighbors and it is possible to propagate information and compute logic functions without physical signal propagation.Another application of crossing minimization algorithms is QCA.The non-adiabatic switching power and polarization error in QCA design circuits is estimated in [1] using a probabilistic modeling tool.A full adder is designed in [2] to enhance the switching level at nanoscale level with the help of high level synthesis.A QCA model is designed in [3] using majority gates and also the model is employed in various parallel prefix adder.
The 2 bit, 3 bit and 4 bit binary to gray converter is described in [4] to analyze the area, power and switching speed occupied by the designed circuit.A 2:1 and 4:1 MUX design of QCA model is designed in [5] to minimize the area and cell count.The QCA full adder with high performance in [6] is used in ripple carry adder which reduces the cell number compare to the other adders.The defect tolerance of circuits and sequential devices implemented by molecular QCA is described in [7]and also defects of logic level characterization is studied in the simulation results.
A unique timing constraint is investigated in [8] for Reset-Set FF and D-FF QCA model.For designing FFs, positive level triggered and falling edge triggered approach are employed in [9] using T-FF for N-bit which offers less power.An XOR gate with 2, 4 and 8-input is designed by utilizing QCA model in [10].It offers less complexity than existing XOR gates.A hybrid full adder is described in [11] using CMOS design and achieved high speed and low power.A reversible multiplier is designed in [12] using CMOS design.It offers less power dissipation.
D latch, T-FF, D-FF, SR latch, 4-bit T-FF register, 2-bitcounter are designed in [13] with low power and sizes.A synchronous counter using D-FF QCA is described in [14] which achieves efficient and robust.A reversible 2X2 crossbar switch is designed in [15] which is suitable for low power application.
The literature survey shows that many researchers introduced different approach for crossing minimization through routing and partitioning.Their results are aimed to produce the calculation uniquely as well as advanced design by QCA.The objective of this work is to explore the new approach with less complication in asynchronous design.Further, the paper is organized by the proposed design in section 2, simulation results in section 3 and conclusion in section 4.

II. METHODS AND MATERIALS
The output which depends on the past output and present input is referred as FF which stores 1 bit information 1 or 0. By an external clock only the first FF is clocked.Then, by the output of the proceedings FF, all subsequent FF are clocked.The reverse operation of the up counter is the down counter.The pulse transmission delay from the FF to FF in the asynchronous counter is high than synchronous counter which causes slower speed.
The clock pulse ripples through FF so the asynchronous counter is also named as ripple counters.Figure 1 shows the 4-bit asynchronous counter which is a simple modification of the UP counter.From 15 to 0 downwards, the 4 bit down counter will counts the numbers.

Fig. 1 4-bit Down Asynchronous counter
The input D of all FF are linked to logic "1" and the input clock of all FFs are cascaded.At every positive edge clock signal the FF will toggles.The input clock is connected to the first FF.The other FF receives the input clock signal from pervious FF output Q in the counter rather than output Q.In the 4-bit down counter Q0, Q1, Q2, Q3 stands for count which is shown in the Fig. 1.If the active edge clock signal takes place then the output of first FF is changed.For instance the current count is 2 then the down counter will compute the next count as 1.The clock input is the origin of variation in the next FF output count.For each clock pulse at the input will decrease the each FF count.Thus the down counter counts from 15, 14, 13…0.Figure 2 (a) and (b) depicts the D-FF symbol and its characteristics equation generation respectively.The characteristic equation for D-FF is Q(t+1) and with the help of this equation the FF are designed using QCA binary wires.

Figure 2 (a) D-FF (b) Generating characteristic equation
Figure 3 illustrates the logic diagram of the D-FF.When the input CP is ON the binary information at the input will shifted to output Q.

Fig.3 Basic logic diagram of the D FF
The output follows the input data when the pulse remains in its state 1.Figure 4 shows the D-FF design using majority gates.Here M1 is AND gate, M2 is OR gate and M3 acts as OR gate.

Fig.4 D-FF using Majority gates
In Fig. 4, P represents polarization.If P=-1 symbolize the logic 0 and P=+1 symbolize the logic 1 binary information.

III. RESULTS AND DISCUSSION
The design of QCA model is different from the conventional CMOS design model due to their clocking approaches.The 4-bit asynchronous down counter using D-FF is designed using QCA design tool.Figure 5 shows the layout of QCA design using D-FF by majority gate.

Figure 5 D FF Layout using Majority gates
This layout has one control clock and one input D. In this layout D is the input CLK is the clock input Q0m is the output.69cells are required for this realization.The 4-bit down asynchronous counter design is shown in Fig. 6.It is constructed using D-FF.

Figure 6 Layout of the 4-bit Asynchronous down counter using D FF
It is a 4-bit counter so it has 4 D-FF.In order to perform the operation of the asynchronous counter it requires 276 cells.The input-output delay of this design is based on the each FF output.Figure 7 shows the simulation waveform for the 4 bit asynchronous counter using new D-FF layouts.

Figure 7 Simulation waveform of 4-bit asynchronous counter using D-FF
In the waveform each input clock pulse will decrease the count of each FF.Thus the down counter counts from 15, 14, 13…0.Here clk and D are the input waveforms, whereas Q0, Q1, Q2, Q3 are the output waveforms.The output Q1 depends on the input clk and D, but the output of for Q2, Q3, Q4 depend on its previous FF output.

IV. CONCLUSION
In this study, 4-bit asynchronous down counter using new D-FF layouts are realized in QCA technology.It can be used in any nano-scale applications with less complex cell design.The functionality and layouts are implemented using the QCA design software tool for 4-bit asynchronous counter.This QCA design models are smaller than the CMOS technology.Here the D-FF is constructed using majority gates with one control input clock.The output of one FF is represented as a clock of consecutive FF in asynchronous counter design.With the help of QCA clock, the correct flow of data information is maintained using QCA wire.In future, the work is extended to dual edge triggered structure based 4-bit asynchronous counter.